These are various forms of local, on-chip memory. Except for the DRAM. 4T (4 transistor) SRAM takes up 4 times the space that regular DRAM does 1T-SRAM seems to be a hybrid of DRAM that allows for ...

The scaling of the 6T SRAM cell is slowing and the surrounding circuitry is getting more complex, so more of the die will be taken up by SRAM at future nodes. The six-transistor static memory cell ...

Zeno’s one-transistor Bi-SRAM uses a single transistor and is ~5× smaller than a conventional SRAM — which uses six-transistor bitcells (6T-SRAM) — at the same technology node One way to look at a ...

Infineon has expanded its wireless memory portfolio with CellularRAM, this is a customised memory solution designed and tailored for mid-range to high-end mobile phone applications. CellularRAM is ...

Imec and Unisantis, a developer of Surrounding Gate Transistor (SGT) semiconductor technology, have revealed significant progress in the development of a process flow targeting an SGT 6T-SRAM cell ...

Leti has combined FD-SOI technology with its 3D CoolCube monolithic stacking technology to create 4T SRAM bitcells with the same functionality level of 6T bitcells, reducing die size by 30%. With SRAM ...

SRAM cells are designed to ensure that the contents of the cell are not altered during read access and the cell can quickly change its state during write operation. These conflicting requirements for ...

Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one ...

Zeno Semiconductor has demonstrated the scalability of its 1-transistor/2-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology to 14nm and 16nm FinFET ...