At process technologies of 0.13 µm and smaller, achieving timing closure for system-on-a-chip (SoC) designs becomes a slippery goal. Ever-tinier interconnects are packed closer together, yielding ...

The most significant development of the new year in electronic design automation may be the advent of integrated, “IC implementation” tool suites that incorporate both logical and physical design. But ...

The relentless pursuit of higher performance and greater functionality has propelled the semiconductor industry through several transformative eras. The most recent shift is from traditional ...

Program leverages Iteris’ traffic signal operations expertise to support city’s goal of improving safety and mobility for all road users, while increasing sustainability. Iteris experts will develop ...

Delay-locked loops (DLLs) are critical components in modern electronic systems, providing robust synchronisation of clock signals in a variety of applications ranging from high-speed communication to ...

For system-on-a-chip designs at 90 and 65 nm, dynamic noise greatly exacerbates the challenge of timing signoff. To accurately examine noise effects, designers need tools that provide an accurate ...