EDN

How SystemVerilog aids design and synthesis

The SystemVerilog extensions to Verilog 2001 have been getting a lot of attention lately, especially the new features designed to support verification and testbench design. But SystemVerilog also ...
Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

Download this article in PDF format. The Portable Stimulus Specification (PSS) is all about reusing commonly used test atoms to create new scenarios more quickly. It saves us from wasting precious ...
EDN

Verific Design Automation’s Netlist Only Parser, Database

Verific Design Automation, best known for its Verilog, SystemVerilog and VHDL parsers and elaborators, today said that its Netlist Only Parser is gaining momentum among electronic design automation ...
Design-Reuse

A Chip IP Integrator for System Level Design

This paper describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool ...